Image above: CarrICool interposer infrastructure supporting heterogeneous microprocessor chip stack with heat removal, power delivery and optical signaling.
MODULAR INTERPOSER ARCHITECTURE PROVIDING SCALABLE HEAT REMOVAL, POWER DELIVERY AND COMMUNICATION
Available packaging solutions cannot support 3D integration density scaling and Beyond-CMOS devices, constraining systemability with respect to energy efficiency, reliability, and computational performance – the key metrics in the many-core, exascale and post-CMOS era. CarrICool demonstrates the smart implementation and the robust manufacturability of advanced More-than-Moore components into a modular and scalable interposer, supporting System-on-Chip and System-in-Package evolution.
All four major packaging elements are implemented on the CarrICool interposer: i) Improved structural and electrical performance is provided by CTE matching and the high wiring density on the interposer. ii) Low thermal gradients, important for high reliability and increased temperature sensitivity of Beyond-CMOS and silicon photonic devices will be achieved by integrated single phase water cooling cavities. iii) A high granulatiry of distributed Buck-converters relying on integrated high quality inductors is supporting energy-efficient power delivery of heterogeneous chip stacks. iv) A disruptive jump in off-chip bandwidth is enabled through low-cost and low-loss passive optical coupling to silicon photonic wave guides.
Advanced characterization and simulation techniques will be implemented involving physics-of-failure-based lifetime modeling and modeling frameworks to provide design-rules for improved system architecture. The performance of the four packaging elements of the modular interposer will be validated on three separate demonstrators and then integrated on the main CarrICool demonstrator package.The consortium pools interdiciplinary excellence, uniting nine partners from industry (1), SMEs (3), institutes (3) and academia (2) from six European countries.
An Advisory Board ensures the alignment of the project goals and supports the definiton of relevant specifications with respect to HPC and mainframe systems.
Advisory Board Members: Forschungszentrum Jülich (FZJ), European Technology Platform for High-Performance Computing (ETP4HPC), IBM Server Technolgy Group (IBM STG)
Silicon Interposer, TSV, liquid cooling, power delivery, Buck-converter, silicon photonic, high-Q, passive coupling