Published Results

The CarrICool consortium will promote the results obtained in the project via the normal routes such as refereed journals and international conferences.

Overview publications:

2017

  • [to be published] T. Brunschwiler et al. “Towards Cube-Sized Compute Nodes: Advanced Packaging Concepts enabling Extreme 3D Integration“, IEDM, San Francisco, December, 2017 (paper)
  • P. A. M. Bezerra, R. K. Aljameh, F. Krismer, J. W. Kolar, A. Sridhar, T. Brunschwiler, T. Toifl. “Analysis and Comparative Evaluation of Stacked-Transistor Half-Bridge Topologies Implemented with 14 nm Bulk CMOS Technology” Proceedings of the 18th IEEE Workshop on Control and Modeling for Power Electronics (COMPEL 2017), Stanford, California, USA, July 9-12, 2017 (paper)
  • Steller W. “High performance fluidic cooling in 3D-Microsystems“, 12th Silicon Saxony Day, Dresden, Germany, 19-20.06.2017 (presentation)
  • Janczyk G., Bieniek T., T. Brunshwiler. “The Modular Interposer Architecture Providing Scalable Heat Removal, Power Delivery and Communication for Many-Core, Exascale and Post-CMOS Era Applications“, European Nanoelectronics Applications, Design & Technology Conference (ATDC17), Dresden, Germany, 09-10.05.2017 (presentation)
  • Janczyk G., Bieniek T., Bajurko P. “CarrICool – the Innovative 3D Interposer Platform for HPC Systems: Analysis, Simulations, Optimization, Practice for Reliability Improvement and Performance Increase“, Informatics, Electronics and Microsystems TechConnect Briefs 2017, Nanoelectronics Chapter 2, 2017, pp. 47-50 (paper)
  • Janczyk G., Bieniek T., Bajurko P., “CarrICool – the Innovative 3D Interposer Platform for HPC Systems: Analysis, Simulations, Optimization, Practice for Reliability Improvement and Performance Increase”, TechConnect World Innovation. Conference & Expo NanoTech 2017, Waszyngton, USA, 14-17.05.2017 (poster)
  • M. Stiebing, D. Vogel, W. Steller, M. J. Wolf, U.Zschenderlein, B. Wunderle “Correlation between mechanical material properties and stress in 3D-integrated silicon microstructures“, Eurosime, Germany, Dresden, April 2017 (paper, keynote)
  • O. Ozsun, S. Paredes, G. Schlottig, and T. Brunschwiler, “Thermal Performance of a Silicon-Interposer with Embedded Fluid Channels Enabling Dual-Side Heat Removal“, Proceedings ITHERM, IEEE, US, Orlando, June 2017 (paper)
  • T. Brunschwiler, G. Schlottig, A. Sridhar, A. La Porta, O. Ozsun, J. Zürcher, R. Strässle, L. Del Carro and P. A. M. Bezerra, “Scalable packaging platform supporting high-performance 3D chip stacks”, Proceedings PanPacific SMTA, Kauai, US, Hawaii, February 2017 (paper, keynote)
  • T. Brunschwiler et al., “Functional Electronic Packaging for Dense Server-System Scaling“, 3D Summit, Grenoble, 2017 (paper)

2016

  • Bieniek T., Janczyk G. “Innovative 3D-IC Interposer Platform for HPC Systems: 3D Analysis, Simulations and Optimization for Reliability Improvement and Performance Increase” X International Forum Innovative technologies foe medicine (ITMED 2016) & 4th International Conference on Nanotechnology in Medicine (NANOMED 2016), Warszawa, Polska, 07-09.11.2016 (poster)
  • Bieniek T., Janczyk G. “CarrICool Project – Modular Interposer Architecture Providing Scalable Heat Removal, Power Delivery and Communication” X International Forum Innovative technologies foe medicine (ITMED 2016) & 4th International Conference on Nanotechnology in Medicine (NANOMED 2016), Warszawa, Polska, 07-09.11.2016 (poster)
  • R. K. Aljameh, P. A. M. Bezerra, F. Krismer, J. W. Kolar, A. Sridhar, T. Brunschwiler, T. Toifl, B. Michel. “Control and Implementation Aspects of a Multiphase Inductor-Based FIVR in 14 nm Bulk CMOS for Microprocessor Applications” Proceedings of the 5th International Workshop on Power Supply On Chip (PwrSoC2016), Madrid, Spain, October 3-5, 2016. (poster)
  • Bieniek T., Janczyk G., Kłos H. “Innovative, Scalable Architecture of Modular Interposer System for Massive Heat Removal, High Power Delivery and Optical Signaling – CarrICool Project”, XII Konferencja Naukowa “Technologia Elektronowa” (ELTE 2016), Wisła, Polska, 11-14.09.2016 (presentation)
  • J. Kleff, G. Schlottig, R. Mrossko, W. Steller, H. Oppermann, J. Keller, T. Brunschwiler “Intra-stack sealing of tier interconnects using the interconnect alloy“,  (ESTC), IEEE, 2016 (paper)
  • A. Sridhar, T. Brunschwiler, “Exploration of Inductor – Based Hybrid Integrated  Voltage Regulator Architectures“,  (ESTC), IEEE, 2016 (paper)
  • Thomas Brunschwiler, Raúl Mroßko, Jürgen Keller, Ozgur Ozsun, and Gerd Schlottig, “Dual-Side Heat Removal by Micro-Channel Cold Plate and Silicon-Interposer with Embedded Fluid Channels” (ESTC), IEEE, 2016 (paper)
  • T.Bieniek, G. Janczyk, “Innovative 3D system development by multifunctional IC interposer platform – Signal Integrity and Thermal Management – solutions for High Performance Computing” ESTC 2016, 6th Electronics System-Integration Technology Conference, September 13 – 16, 2016, World Trade Center, Grenoble, France (paper)
  • M. Stiebing, D. Vogel, E. Lörtscher, W. Steller, M. J. Wolf, T. Brunschwiler, and B. Wunderle, “TSV- and Interconnect-induced Stress Investigations in 3D Integrated Silicon Microstructures“, EUROSIME, Montpellier, France, 2016 (paper)
  • G. Schlottig, T. Brunschwiler. “Lid-Integral Cold-Plate Topology: Integration, Performance, and Reliability“, Journal of Electronic Packaging 138 (1), 10.1115/1.4032493, 2016 (journal paper)
  • T. Brunschwiler, A. Sridhar, C. L. Ong, G. Schlottig “Benchmarking Study on the Thermal Management Landscape for Three-Dimensional Integrated Circuits: From Back-Side to Volumetric Heat Removal“, Journal of Electronic Packaging 138 (1) 10.1115/1.4032492, 2016. (journal paper)

2015

  • Bieniek T., Janczyk G., “Modular interposer architecture providing scalable heat removal, power delivery, and communication (CarrICool)” ITMED 2015: 9th International Forum on Innovative Technologies for Medicine, 3-5.12.2015, Suprasl, Poland, additionally project advertisement in forum catalogue (ITE) (poster)
  • M. Haupt, O. Ozsun, T. Brunschwiller, J. Keller, “Heat Transfer Modelling of a Dual-Side Cooled Microprocessor Chip Stack with Embedded Micro-Channels“, Proc. THERMINIC 2015, Paris, France 2015. (paper)
  • Pedro A. M. Bezerra, Florian Krismer, Toke M. Andersen, Johann W. Kolar, Arvind Sridhar, Thomas Brunschwiler, Thomas Toifl, Mohamed Jatlaoui, Frederic Voiron, Zoran Pavlovic, Ningning Wang, Nicolas Cordero, Caroline Rabot, Cian O’ Mathuna. “Modeling and Multi-Objective Optimization of 2.5D Inductor-Based Fully Integrated Voltage Regulators for Microprocessor Applications” Proceedings of the 1st Southern Power Electronics Conference (SPEC 2015), Fortaleza, Brazil, November 29-December 2, 2015. (paper)
  • T. Bieniek, G. Janczyk, “Modular interposer architecture providing scalable heat removal, power delivery, and communication (CarrICool)” poster in ITE stand during the COMS 2015: 20th edition of the annual international conference on commercializing micro- and nanotechnology, 13-16.09.2015, Krakow, Poland, http://coms2015.eu; project advertisement in Conference folder; project advertisement during all conference, printed and on CD material about CiC on the table (ITE)
  • T. Brunschwiler, G. Schlottig, J. Zürcher, S. Zimmermann, B. Burg, A. Sridhar, P. Bezerra, S. Paredes, P. Ruch, T. Tick, S. Oggioni, B. Michel , “On the path towards scalable 3D integration by advanced packaging“, D43D, 2015 (presentation)
  • T. Brunschwiler, A. Sridhar, C. L. Ong, and G. Schlottig, “Benchmarking Study on the Thermal Management Landscape for 3D ICs: from Back-Side, to Volumetric Heat Removal“, InterPACK, San Francisco, CA, 2015 (paper)
  • G. Schlottig, M.De Fazio, W.Escher, P.Granatieri, V.D.Khanna, T. Brunschwiler,  “Lid-Integral Coldplate Topology: Integration, Performance, and Reliability“, InterPACK, San Francisco, CA, 2015 (paper)
  • Thomas Brunschwiler et al., “Thermal-Packaging Landscape from back-side to volumetric heat removal“, Advances in thermal management, Denver, 2015 (presentation)
  • P. A. M. Bezerra, T. Andersen, F. Krismer, J. W. Kolar. “Multi-objective Optimization of Fully Integrated Voltage Regulators: Switched Capacitor and Inductor-Based Converters” ECPE PowerSoC Workshop “µPE: Powering Low-Power Systems”, Ismaning/Munich, Germany, June 16-17, 2015. (workshop presentation)
  • Bieniek T., Janczyk G. “Thermo-Mechanical Modelling of Innovative Power Distribution Modules for Stacked ICs”, Smart Engineering of New Materials (SNEM 2015) oraz Microtechnology and Thermal Problems in Electronics (MicroTherm 2015 ), Łódź, Polska, 22-25.05.2015 (poster)
  • Bieniek T., Janczyk G. “CarrICool – Modular Interposer Architecture Providing Scalable Heat Removal, Power Delivery and Communication”, 9th International Forum Science and Technology Days Poland – East IFST 2015, Supraśl, Polska, 28-30.05.2015 (poster)
  • M. Stiebing, D. Vogel, W. Steller, M. J. Wolf, B. Wunderle, “Challenges in the Reliability of 3D Integration using TSVs“, Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE), 2015 16th International Conference on , Budapest, 2015 (paper)

2014

  • T. Bieniek, G. Janczyk, “CarrICool – Modular interposer architecture providing scalable heat removal, power delivery, and communication“. ITMED 2014, 4-6 December 2014, Supraśl (poster)